Pearson Edexcel iGCSE CS Revision Portal

Lesson 1: Computer Systems & Architecture

Recommended Duration: 80 Minutes | Syllabus Focus: Central Processing Unit (CPU) & Memory Hierarchy

1.1 The Von Neumann CPU Architecture

Under the Von Neumann architecture, both instructions and data are stored together in a single shared memory unit (RAM). The CPU fetches instructions, decodes them, and executes them in sequence.

PC

Program Counter

Holds the memory address of the next system instruction to be fetched from RAM. It automatically increments by 1 on every fetch phase.

MAR

Memory Address Register

Stores the memory address of the data or instruction currently being read from or written to RAM.

MDR

Memory Data Register

Acts as a temporary buffer holding the actual instruction, digital character, or value newly fetched from memory, or preparing to be saved back into memory.

CIR

Current Instruction Register

Holds the active instruction currently undergoing decoding by the Control Unit (CU) before execution.

ACC

Accumulator

Stores the intermediate mathematical calculations and logical comparisons computed inside the Arithmetic and Logic Unit (ALU).

CU & ALU

Control Unit & Logic Unit

The CU generates clock synchronization pulses to sequence instructions. The ALU handles physical logical calculation execution steps.

System Buses & Directionality

A system bus is a set of parallel physical wires connecting the CPU to memory and input/output interfaces. Pearson Edexcel expects deep familiarity with these three buses:

Address Bus: Unidirectional

Can only send address codes out from the CPU to external memory locations. Memory never sends back addresses to the CPU.

Data Bus: Bidirectional

Carries instruction data, character representations, and operands back and forth between registers and RAM memory chips.

Control Bus: Bidirectional

Transmits control, clock pulses, read/write commands, and hardware interrupts between modules to avoid collision states.

Chronological Sequence of the Fetch-Decode-Execute Cycle

Review how register-level states update during execution. Knowing this step-by-step sequence is critical for scoring maximum marks on design/explain questions.

STAGE 1

PC $\rightarrow$ MAR

The memory address of the next planned instruction is copied from the PC into the MAR via the address bus.

STAGE 2

RAM $\rightarrow$ MDR

The CPU requests memory contents. The instruction at that address is sent across the bidirectional Data Bus and stored temporarily inside the MDR.

STAGE 3

MDR $\rightarrow$ CIR & Increment

The instruction moves from MDR to CIR. Concurrently, the PC increments by 1 to point safely to the next sequential location.

STAGE 4

Decode & Execute

The Control Unit decodes the instruction inside the CIR. The necessary signals are sent, and the ALU handles physical calculations or logical operations.

1.2 The Memory Hierarchy: RAM, ROM, Secondary & Tertiary Storage

Primary Storage (RAM, ROM, and CPU Cache)

RAM (Random Access Memory)

Volatile primary storage with fast read/write speeds. It holds running programs and actively executing background OS code. Uses dynamic RAM (DRAM, cheaper, requires refreshing) and static RAM (SRAM, faster, used for high-speed CPU caches).

ROM (Read-Only Memory)

Non-volatile primary storage. It holds startup boot software (BIOS/UEFI or basic firmware). Its contents are permanent and cannot be deleted or written to under typical operating conditions.

Cache Memory

Extremely high-speed static RAM built directly into the CPU chip. It stores frequently used instructions so the CPU doesn't have to wait for slower system RAM.

Secondary Storage Media Mechanics

Magnetic Media (HDD)

Spins circular, rigid platters partitioned into tracks and sectors. An actuator arm positions an electromagnetic read/write head to map polarization directions as binary 1s/0s. Magnetic disks are highly susceptible to physical shocks and wear.

Solid State Media (SSD)

Non-volatile storage with no moving parts. Relies on NAND Flash memory arrays and floating gate transistors to capture electrons. Highly shock-resistant, low-power, lightweight, with fast boot speeds.

Optical Storage (Blu-Ray/DVD/CD)

Uses high-precision lasers to read pits and lands pressed into a circular disc as it rotates. Poor read/write speeds, highly prone to scratching, but extremely cheap to manufacture and distribute.

Medium Type	Mechanical Parts?	Average Read Speed	Typical Cost per GB	Relative Durability
Magnetic (HDD)	Yes (Spinning platters)	Slow (~150 MB/s)	Very Low	Low (Scratches/Shock)
Solid State (SSD)	No (Electronic)	Very Fast (500-3500 MB/s)	Medium to High	High (No physical parts)
Optical (Blu-Ray/DVD)	Yes (Laser rotates disc)	Very Slow	Extremely Low	Poor (Easily scratched)

Lesson 1 Exam Prep Worksheets

Q1: Explain why a computer requires both RAM and ROM. (4 Marks)

Exam Tip: For an Edexcel 4-mark question, ensure clear logical expansion using correct terminology (volatile, non-volatile, read/write, read-only).

RAM is volatile, meaning it loses all saved contents when power is turned off (1).
RAM holds dynamically executing apps, programs, and working data for CPU processing (1).
ROM is non-volatile, which means it permanently preserves data even without electric supply (1).
ROM stores basic bootstrap startup codes (BIOS/firmware) to load the operating system (1).

Q2: A student suggests that the Address Bus must carry memory feedback parameters back to the CPU. Evaluate this claim. (2 Marks)

The claim is incorrect:

The Address Bus is strictly **unidirectional** (1).
It can only send instructions/location codes from the CPU to the memory, never from memory to CPU (1).

Lesson 2: Data Representation & Modeling

Recommended Duration: 80 Minutes | Syllabus Focus: Storage Units, Binary Calculations, Character Encoding, Simulations

2.1 Number Bases & Signed Negative Two's Complement

Computers process electrical states, necessitating binary representation. To handle negative numbers efficiently, modern systems use **Two's Complement** instead of simple sign-and-magnitude bits. This resolves structural issues like the "double zero" ($+0$ vs $-0$) anomaly.

Converting Denary to Two's Complement

Standard method: To write a negative value like $-44$ into an 8-bit register:

Write down the positive value in binary: $44 \rightarrow \text{00101100}$
Flip all bits (complement) (NOT operation): $\text{11010011}$
Add 1 to the result: $\text{11010011} + 1 = \text{11010100}$

Validation Place Values: $-128, 64, 32, 16, 8, 4, 2, 1$
$-128 \times 1 + 64 \times 1 + 32 \times 0 + 16 \times 1 + 8 \times 0 + 4 \times 1 + 2 \times 0 + 1 \times 0 = -44$. Correct!

Arithmetic Shifts & Overflow Errors

Shifting bits mathematically multiplies or divides numbers quickly.

Arithmetic Shift Left (×2): Shifts all bits left. A `0` is introduced at the right. The MSB (sign bit) is kept or updated correctly based on the operation.
Overflow Error: Occurs when the mathematical result of an addition or shift calculation is too large to fit in the register's maximum bit capacity (e.g., adding $+120$ and $+15$ inside an 8-bit register). The "extra" 9th bit is discarded, producing mathematically incorrect results.

2.2 File Size Calculation Expressions

Pearson Edexcel assessment guidelines test your ability to construct mathematical expressions for file sizes using base-2 standard binary prefixes (KiB, MiB).

Image File Size in Mebibytes (MiB)

$$\text{Size} = \frac{\text{Width} \times \text{Height} \times \left(\frac{\text{Color Depth}}{8}\right)}{1024 \times 1024}$$

Width & Height: Image size in pixels.

Color Depth: Number of bits allocated per pixel ($2^n = \text{colors}$).

Denominator: Divide by 8 (bits to bytes) and then by $1024 \times 1024$ (bytes to KiB to MiB).

Sound File Size in Mebibytes (MiB)

$$\text{Size} = \frac{\text{Sample Rate (Hz)} \times \text{Resolution (bits)} \times \text{Duration (s)}}{8 \times 1024 \times 1024}$$

Sample Rate: Number of digital samples recorded per second (measured in Hertz, Hz).

Sample Resolution: Number of bits per sample (bit depth).

Duration: Total duration of track in seconds.

2.3 Character Sets & Computational Models

ASCII vs. Unicode Character Sets

Computers do not store text directly; they map numbers to characters. A **Character Set** defines this matching table.

ASCII (7 or 8 bits): Restricts representation to 128 or 256 unique English characters. Saves storage space but cannot map non-English alphabets.
Unicode (Up to 32 bits): Universal encoding standard. Can represent all historical and active languages worldwide (including emojis). Requires more storage space per character.

Computational Simulations & Models

A computer simulation runs real-world math rules digitally to evaluate complex scenarios.

Key Benefits: Safer (testing aerodynamic crashes digitally), cheaper than constructing physical mockups, and faster (predicting years of weather in seconds).
Multi-Agent Model: Complex systems modeling where multiple autonomous computing nodes ("agents") communicate to test cooperative operations.

Lesson 2 Exam Prep Worksheets

Q1: Create a mathematical expression calculating the exact file size in MiB of a 4K camera output capture: 3840 pixels wide by 2160 pixels high, capturing colors with 24-bit color depth. (3 Marks)

Expression components needed for 3 Marks:

$$\frac{3840 \times 2160 \times \left(\frac{24}{8}\right)}{1024 \times 1024}$$

Numerator correctly lists resolution: $3840 \times 2160$ (1).
Numerator correctly divides bit depth: $\frac{24}{8}$ (or simply $\times 3$) to convert to bytes (1).
Denominator includes $1024 \times 1024$ (or $1024^2$ or $2^{20}$) to scale bytes to Mebibytes (1).

Q2: Convert the 8-bit Two's Complement binary value `1100 0011` into a denary integer. Show your work. (2 Marks)

Step-by-step conversion:

Place values: -128, 64, 32, 16, 8, 4, 2, 1

Sum = (-128 * 1) + (64 * 1) + (2 * 1) + (1 * 1) (1)

Answer = -61 (1)

Lesson 3: Algorithms, Logic & Code Debugging

Interactive Syllabus Revisions Worksheet practice questions (May 2026 update)

3.1 Q1: Pseudocode Trace Tables

Analyze the following pseudocode validation algorithm designed to calculate the digit sum of an input and verify if its length meets structural requirements. Complete the interactive trace tables below.

# Pseudocode Algorithm Specification

01 RECEIVE code FROM KEYBOARD

03 SET digitTotal TO 0

04 SET position TO 1

05 SET validLength TO TRUE

07 WHILE code > 0

08 SET digit TO code MOD 10

09 SET digitTotal TO digitTotal + digit

10 SET code TO code DIV 10

11 SET position TO position + 1

12 END WHILE

14 IF position <> 5 THEN

15 SET validLength TO FALSE

16 END IF

18 IF validLength = TRUE AND digitTotal MOD 3 = 0 THEN

19 SEND "valid" TO DISPLAY

20 ELSE

21 SEND "invalid" TO DISPLAY

22 END IF

Trace Table A: Input 1230

Row	code	digit	digitTotal	position	validLength	digitTotal MOD 3	Output
1
2
3
4
5

Trace Table B: Input 7258

Row	code	digit	digitTotal	position	validLength	digitTotal MOD 3	Output
1
2
3
4
5

3.2 Q5: Smart Doorbell Logic System & Truth Tables

System Logical Specification

A smart home sends a notification when motion is detected (M = 1) OR the doorbell button is pressed (B = 1), AND quiet mode is not turned on (Q = 0, meaning NOT Q = 1).

Logic Expression: $$(M \text{ OR } B) \text{ AND NOT } Q$$

Interactive Verification Truth Table

M	B	Q
0	0	0
0	0	1
0	1	0
0	1	1
1	0	0
1	0	1
1	1	0
1	1	1

3.3 Q6: Programming Constructs & Code Errors

Q6(a): Python Equivalence Operator

Identify the operator used to check if two values are equal in Python.

Q6(b): Find and Fix the Three Programming Errors

The program below should check sensor values inside readings and count high/low readings. However, it contains exactly **three syntax/logic errors**. Analyze the code and fix the lines below.

# Buggy Sensor Analyzer Program

01 readings = ["high", "low", "high", "normal", "low", "high", "low"]

02

03 highCount = 0

04 lowCount = 0

05

06 for reading in readings:

07 if reading == "high"

08 highCount = highCount + 1

09 elif reading = "low":

10 lowCount = lowCount + 1

11

12 print("High:", highCount)

13 print("Low:", LowCount)

14 print("Total:", highCount + lowCount)

Code Repair Zone

Error 1 (Line 07): Syntax

Error 2 (Line 09): Logic Comparison

Error 3 (Line 13): Variable Naming/Casing

Teacher & Student Exam Resources

Edexcel Past Paper

Official Pearson Edexcel iGCSE Computer Science Paper 1 featuring theory, data storage, and systems architecture questions.

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Edexcel Mark Scheme

Complete solutions, grading criteria, and examiner steps for self-correction. Access is restricted by password protection.

Interactive Syllabus Tracker

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Personal Edexcel Revision Checklist

Track your progress and export a certified PDF as proof of study.

Student Name:

Unit 1: Computer Systems

RAM vs. ROM Functions Volatile processes vs. BIOS bootstrap startup codes

Von Neumann Registers PC, MAR, MDR, CIR, and ACC interactions

System Bus Properties Address Bus, Data Bus, and Control Bus behaviors

Unit 2: Data & Modeling

Two's Complement Sign bits and decoding signed negative integer binaries

File Size Calculations Resolution, sampling rate, duration equations in MiB

Simulations & Modeling Evaluating risks, variables, and multi-agent model logic

Unit 3: Algorithms & Logic

Algorithmic Tracing Tracing modulo and integer division loops row-by-row

Logic Gates & Truth Tables Analyzing complex logic rules and truth state tables

Syntax & Logic Debugging Finding comparisons, structure and scoping bugs in code

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